InCore 5G Base Station SoC Successfully Taped Out, India's Design Capability Soars
July 29, 2026, Bangalore – India's leading semiconductor design service company InCore Semiconductors today announced that its self-developed 5G base station AI-accelerated SoC (system-on-chip) has been successfully taped out and is expected to enter mass production in Q4 2026. The chip uses an advanced process node, integrating a neural network acceleration core, digital signal processing unit, and 5G NR baseband protocol stack. Designed specifically for Open RAN (O-RAN) architecture, it can significantly reduce base station power consumption and improve edge inference efficiency. InCore CEO Rajesh Garg stated at the press conference: 'This is the first time an Indian local design team has achieved a fully autonomous 5G communication SoC from architecture definition to physical implementation. We have already received preliminary procurement intent from Indian telecom operator Bharti Airtel and two Tier-1 operators in Southeast Asia.'
Asia-Pacific Custom Chip Market Continues to Heat Up
InCore's success reflects the profound transformation of the semiconductor design service industry in the Asia-Pacific region. According to the latest report from market research firm IDC, the Asia-Pacific ASIC (Application-Specific Integrated Circuit) design service market grew 34% year-on-year in Q2 2026, reaching $4.7 billion, with communication infrastructure and AI accelerators accounting for 65% of the share. Taiwan and South Korea still dominate high-end process design, but design firms in India, Vietnam, and Malaysia are rapidly gaining market share in mature nodes (28nm and above) and mid-range nodes (16nm-7nm) due to lower labor costs and flexible engineering support. InCore's tape-out uses TSMC's 12nm FinFET process, targeting the balance of cost and energy efficiency required for 5G base stations.
Design Service Model Innovation: From Turnkey to Chiplet Collaboration
Notably, InCore's 5G SoC is not entirely self-developed but adopts a flexible 'Chiplet + advanced packaging' strategy. According to the company's VP of Technology, the chip comprises a digital baseband chiplet designed by InCore and an analog RF chiplet provided by a Korean company, interconnected via the UCIe standard, and finally packaged by ASE using 2.5D packaging. This collaboration model is becoming common among small and medium-sized design companies in Asia-Pacific: they do not need to build extensive IP libraries and testing capabilities but can rapidly deliver custom chips through ecosystem collaboration. Industry analysts point out that as Moore's Law slows, the Chiplet architecture will drive the formation of a 'design company - chiplet supplier - packaging house' triangular collaboration system in the Asia-Pacific region, and InCore's successful tape-out provides key validation for this model.
Investment Perspective: Layout Logic Under the Custom Chip Wave
For investors, InCore's milestone reinforces three trends: first, the need for domestic substitution in communication infrastructure (especially in India and Southeast Asia) will continue to drive local design service orders; second, the maturity of the O-RAN ecosystem lowers the design threshold for base station chips, allowing more small and medium-sized design companies to participate; third, packaging houses with Chiplet integration capabilities (such as ASE and JCET) will benefit from spillover design service demand. However, risks remain: global semiconductor capital expenditure is shifting towards AI GPUs and HBM, potentially squeezing tape-out capacity for communication ASICs; Indian design companies still need to accumulate experience in IP compliance and yield ramp-up. It is recommended to focus on chiplet suppliers closely collaborating with InCore and third-party IP companies holding foundational Chiplet patents.
Hidden Link with the Casting Industry
Although InCore itself is a fabless design company, its successful tape-out relies indirectly on the Asia-Pacific casting industry. On one hand, high-precision metal heat sinks, shielding covers, and other die-cast parts required for chip packaging are supplied by casting companies in Taiwan and mainland China. As 5G base station power consumption declines, the proportion of aluminum-magnesium alloy castings in thermal management solutions increases. On the other hand, the precision requirements of semiconductor equipment (such as lithography machine components) push casting processes towards micron-level accuracy. According to the OceanRing Casting Market Index, capacity utilization of precision casting in the Asia-Pacific region rose to 89% in Q2 2026, with some squeeze casting lines even experiencing capacity crowding, positively correlated with the surge in semiconductor back-end packaging demand.
Industry Data at a Glance
- 2026 Asia-Pacific ASIC Design Service Market Size: $4.7 billion (+34% YoY)
- InCore 5G SoC Tape-Out Process: TSMC 12nm FinFET
- Expected Mass Production: Q4 2026
- O-RAN Base Station Penetration: Global forecast 40% by 2027 (Source: Dell'Oro)
InCore's breakthrough is not only a milestone for Indian semiconductor design but also reveals the trend of the Asia-Pacific semiconductor industry evolving from 'manufacturing concentration' to 'design dispersion'. The demand for customized, small-batch, and fast-iteration designs is pushing design companies across Asia into the spotlight, while casting, packaging, and other supporting links become hidden infrastructure harvesting this dividend.
